In recent years, the progress of semiconductor integrated circuits is remarkable, and data processing functions and data that can be embedded in a chip are dramatically increasing. However, as for a semiconductor device that requires confidentiality of data or the like, such as an IC card equipped with an IC chip, it is important to ensure the security thereof in promoting full-scale spread of this kind of semiconductor device.
To be specific, it is a great threat that this type of LSI for which security is required is operated with a frequency out of an allowable range being inputted to the LSI, and thereby secret information is leaked out. As a countermeasure against such threat, a frequency sensor that detects frequencies of an input clock signal and the like has increasingly become important (for example, refer to Patent Document 1: European Patent No. 1136830 (Pages 2-4, FIGS. 1-4), and Patent Document 2: Japanese Published Patent Application No. Hei. 9-16281 (Pages 5-8, FIGS. 1-2)).
Hereinafter, an example of a conventional frequency sensor will be described.
FIGS. 17 and 18 are diagrams illustrating a conventional frequency sensor and signal waveforms.
In FIG. 17, this frequency sensor includes an edge detection circuit 171, an n-bit counter (n: integer not less than 2) 172, and a state storage unit 173.
A reference clock signal 174 is inputted to the n-bit counter 172 and the state storage unit 173. A clock input signal 175 is inputted to the edge detection circuit 171. Further, an edge detection output signal 176 is outputted from the edge detection circuit 171 to the state storage unit 173. A reset signal 177 is inputted to the edge detection circuit 171, the n-bit counter 172, and the state storage unit 173. A state reset signal 178 is outputted from the n-bit counter 172 to the state storage unit 173.
Hereinafter, a description will be given of the operation of the frequency sensor constituted as described above, with reference to FIGS. 17 and 18.
First of all, when it is assumed that the limit values of the allowable frequency range of a system equipped with this frequency sensor are Fmin and Fmax, the allowable time for one cycle is within Tmin=1/Fmin and larger than Tmax=1/Fmax, that is, the count value of the n-bit counter 172 is within nL and larger than nH (nL>nH).
The edge detection circuit 171 detects rising edges of the clock input signal 175. The n-bit counter 172 is reset by the reset signal 177, and counts up by “1” at each rising edge of the reference clock signal 174. The state storage unit 173 checks whether the count value reaches nL or not, and continues count-up at the rising edges of the reference clock signal 174 when the count value has not yet reached nL. When the count value has reached nL due to the continued count-up, it means that the time for one cycle is larger than Tmin. That is, since the frequency is smaller than Fmin, the n-bit counter 172 outputs a state reset signal 178, whereby the state storage unit 173 outputs a low frequency detection signal LF_Alarm. When a rising edge of the clock input signal 175 is detected although the count value has not yet reached nL, the state storage unit 173 checks whether the count value is smaller than nH or not. When the count value is larger than nH, it means that the clock input signal 175 is within the allowable frequency range, and the n-bit counter 172 is reset. When the count value is smaller than nH, it means that the clock input signal 175 is higher than the allowable frequency range, and the state storage unit 173 outputs a high frequency detection signal HF_Alarm. Then, the processing is repeated from the first step by the reset signal 177.
As described above, it is detected as to whether the clock input signal is within the allowable frequency range or not, by generating a reference clock and counting the same with the counter.
Setting of detection frequencies is changed by changing the values of nH and nL.